rev. a a adg619/adg620 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. cmos 5 v/+5 v 4 single spdt switches functional block diagram in adg619/adg620 s2 s1 d switches shown for a logic 1 input features 6 (max) on resistance 0.8 (max) on resistance flatness 2.7 v to 5.5 v single supply 2.7 v to 5.5 v dual supply rail-to-rail operation 8-lead sot-23 package, 8-lead msop package typical power consumption (<0.1 w) ttl/cmos compatible inputs applications automatic test equipment power routing communication systems data acquisition systems sample-and-hold systems avionics relay replacement battery-powered systems general description the adg619 and the adg620 are monolithic, cmos spdt (single pole, double throw) switches. each switch conducts equally well in both directions when on. the adg619/adg620 offer low on resistance of 4 ? , which is matched to within 0.7 ? between channels. these switches also provide low power dissipation yet give high switching speeds. the adg619 exhibits break-before-make switching action, thus preventing momentary shorting when switching channels. the adg620 exhibits make-before-break action. the adg619/adg620 are available in an 8-lead sot-23 pack- age and an 8-lead msop package. product highlights 1. low on resistance (r on ) (4 ? typ). 2. dual 2.7 v to 5.5 v or single 2.7 v to 5.5 v supply. 3. low power dissipation. cmos construction ensures low power dissipation. 4. fast t on /t off . 5. tiny 8-lead sot-23 package and 8-lead msop p ackage. table i. truth table for the adg619/adg620 in switch s1 switch s2 0 on off 1 off on
rev. a e2e adg619/adg620especifications b version parameter +25 c e40 c to +85 c unit test conditions/comments analog switch analog signal range v ss to v dd vv dd = +4.5 v, v ss = e4.5 v on resistance (r on )4 typ v s = 4.5 v, i s = e10 ma; 68 max test circuit 1 on resistance match between channels ( r on ) 0.7 typ v s = 4.5 v, i s = e10 ma 1.1 1.35 max on resistance flatness (r flat (on) ) 0.7 0.8 typ v s = 3.3 v, i s = e10 ma 1.15 1.2 max leakage currents v dd = +5.5 v, v ss = e5.5 v source off leakage i s (off) 0.01 na typ v s = 4.5 v, v d = 4.5 v; 0.25 1n a max test circuit 2 channel on leakage i d , i s ( on) 0.01 na typ v s = v d = 4.5 v; test circuit 3 0.25 1na max digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 2 pf typ dynamic characteristics 2 adg619 t on 80 ns typ r l = 300 , c l = 35 pf 120 155 ns max v s = 3.3 v; test circuit 4 t off 45 ns typ r l = 300 , c l = 35 pf 75 90 ns max v s = 3.3 v; test circuit 4 break-before-make time delay, t bbm 40 ns typ r l = 300 , c l = 35 pf 10 ns min v s1 = v s2 = 3.3 v; test circuit 5 adg620 t on 40 ns typ r l = 300 , c l = 35 pf 65 85 ns max v s = 3.3 v; test circuit 4 t off 200 ns typ r l = 300 , c l = 35 pf 330 400 ns max v s = 3.3 v; test circuit 4 make-before-break time delay, t mbb 160 ns typ r l = 300 , c l = 35 pf 10 ns min v s = 0 v; test circuit 6 charge injection 110 pc typ v s = 0 v, r s = 0 , c l = 1 nf; test circuit 7 off isolation e67 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 8 channel-to-channel crosstalk e67 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 10 bandwidth e3 db 190 mhz typ r l = 50 , c l = 5 pf; test circuit 9 c s (off) 25 pf typ f = 1 mhz c d, c s (on) 95 pf typ f = 1 mhz power requirements v dd = +5.5 v, v ss = e5.5 v i dd 0.001 a typ digital inputs = 0 v or 5.5 v 1.0 a max i ss 0.001 a typ digital inputs = 0 v or 5.5 v 1.0 a max notes 1 temperature range is as follows: b version, e40 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. dual supply 1 (v dd = +5 v 10%, v ss = e5 v 10%, gnd = 0 v. all specifications e40 c to +85 c, unless otherwise noted.)
rev. a e3e adg619/adg620 single supply 1 (v dd = +5 v 10%, v ss = 0 v, gnd = 0 v. all specifications e40 c to +85 c, unless otherwise noted.) b version parameter +25 c e40 c to +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd vv dd = 4.5 v, v ss = 0 v on resistance (r on )7 typ v s = 0 v to 4.5 v, i s = e10 ma; 10 12.5 max test circuit 1 on resistance match between channels ( r on ) 0.8 typ v s = 0 v to 4.5 v, i s = e10 ma 1.1 1.3 max on resistance flatness (r flat (on) ) 0.5 0.5 typ v s = 1.5 v to 3.3 v, i s = e10 ma 1 max leakage currents v dd = 5.5 v source off leakage i s (off) 0.01 na typ v s = 1 v/4.5 v, v d = 4.5 v/1 v; 0.25 1n a max test circuit 2 channel on leakage i d , i s ( on) 0.01 na typ v s = v d = 1 v/4.5 v; 0.25 1n a max test circuit 3 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 2 pf typ dynamic characteristics 2 adg619 t on 120 ns typ r l = 300 , c l = 35 pf 220 280 ns max v s = 3.3 v; test circuit 4 t off 50 ns typ r l = 300 , c l = 35 pf 75 110 ns max v s = 3.3 v; test circuit 4 break-before-make time delay, t bbm 70 ns typ r l = 300 , c l = 35 pf, 10 ns min v s1 = v s2 = 3.3 v; test circuit 5 adg620 t on 50 ns typ r l = 300 , c l = 35 pf 85 110 ns max v s = 3.3 v; test circuit 4 t off 210 ns typ r l = 300 , c l = 35 pf 340 420 ns max v s = 3.3 v; test circuit 4 make-before-break time delay, t mbb 170 ns typ r l = 300 , c l = 35 pf 10 ns min v s = 3.3 v; test circuit 6 charge injection 6 pc typ v s = 0 v, r s = 0 , c l = 1 nf; test circuit 7 off isolation e67 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 8 channel-to-channel crosstalk e67 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 10 bandwidth e3 db 190 mhz typ r l = 50 , c l = 5 pf; test circuit 9 c s (off) 25 pf typ f = 1 mhz c d , c s (on) 95 pf typ f = 1 mhz power requirements v dd = 5.5 v i dd 0.001 a typ digital inputs = 0 v or 5.5 v 1.0 a max notes 1 temperature range is as follows: b version, e40 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice.
rev. a adg619/adg620 e4e absolute maximum ratings 1 (t a = 25 c, unless otherwise noted.) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +6.5 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to e6.5 v analog inputs 2 . . . . . . . . . . . . . . . v ss e 0.3 v to v dd + 0.3 v digital inputs 2 . . . . . . . . . . . . . . . . . e0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma (pulsed at 1 ms, 10% duty cycle max) continuous current, s or d . . . . . . . . . . . . . . . . . . . . 50 ma operating temperature range industrial (b version) . . . . . . . . . . . . . . . e40 c to +85 c storage temperature range . . . . . . . . . . . . e65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c msop package ja thermal impedance . . . . . . . . . . . . . . . . . . . . 206 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . . . . 44 c/w sot-23 package ja thermal impedance . . . . . . . . . . . . . . . . . . 229.6 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . 91.99 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . . 300 c ir reflow, peak temperature . . . . . . . . . . . . . . . . . . . 220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at in, s, or d will be clamped by internal diodes. current should be limited to the maximum ratings given. ordering guide temperature package package branding model range description option information * adg619brm e40 c to +85 cm icro small outline package (msop) rm-8 svb adg619brm-reel e40 c to +85 cm icro small outline package (msop) rm-8 svb adg619brm-reel7 e40 c to +85 cm icro small outline package (msop) rm-8 svb ADG619BRT-R2 e40 c to +85 cp lastic surface mount package (sot-23) rt-8 svb adg619brt-reel e40 c to +85 cp lastic surface mount package (sot-23) rt-8 svb adg619brt-reel7 e40 c to +85 cp lastic surface mount package (sot-23) rt-8 svb adg620brm e40 c to +85 cm icro small outline package (msop) rm-8 swb adg620brm-reel e40 c to +85 cm icro small outline package (msop) rm-8 swb adg620brm-reel7 e40 c to +85 cm icro small outline package (msop) rm-8 swb adg620brt-reel e40 c to +85 cp lastic surface mount package (sot-23) rt-8 swb adg620brt-reel7 e40 c to +85 cp lastic surface mount package (sot-23) rt-8 swb * branding on sot-23 and msop packages is limited to three characters due to space constraints. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg619/adg620 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin configurations 8-lead sot-23 (rt-8) top view (not to scale) 8 7 6 5 1 2 3 4 nc = no connect d s1 nc v dd s2 gnd in v ss adg619/ adg620 8-lead msop (rm-8) top view (not to scale) 8 7 6 5 1 2 3 4 nc = no connect d s1 nc v dd s2 gnd in v ss adg619/ adg620
rev. a e5e adg619/adg620 terminology mnemonic description v dd most positive power supply potential. v ss most negative power supply in a dual-supply application. in single-supply applications, this should be tied to ground at the device. gnd ground (0 v) reference. i dd positive supply current. i ss negative supply current. s source terminal. may be an input or output. dd rain terminal. may be an input or output. in logic control input. r on ohmic resistance between d and s. dr on on resistance match between any two channels, i.e., r on m ax e r on min. r flat (on) flatness is defined as the difference between the maximum and minimum value of on re sistance as measured over the specified analog signal range. i s (off) source leakage current with the switch off. i d , i s (on) channel leakage current with the switch on. v d (v s )a nalog voltage on terminals d, s. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. c s (off) off switch source capacitance. c d , c s (on) on switch capacitance. t on delay between applying the digital control input and the output switching on. t off delay between applying the digital control input and the output switching off. t mbb on time is measured between the 80% points of both switches, when switching from one address state to another. t bbm off time or on time is measured between the 90% points of both switches, when switching from one address state to another. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switch ing. crosstalk a m easure of unwanted signal coupled through from one channel to another as a result of parasitic c apacitance. off isolation a measure of unwanted signal coupling through an off switch. bandwidth the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. t ypical performance characteristics v d , v s e v e3 5 13 on resistance e 8 0 3 2 5 e5 e1 7 1 6 4 e2 2 4 e4 0 t a = 25 c v dd , v ss = 2.5v v dd , v ss = 3v v dd , v ss = 3.3v v dd , v ss = 4.5v v dd , v ss = 5v tpc 1. on resistance vs. v d (v s ) (dual supply) v d , v s e v 15 34 on resistance e 18 0 4 14 10 0 2 16 6 2 12 8 t a = 25 c v ss = 0v v dd = 2.7v v dd = 3v v dd = 3.3v v dd = 4.5v v dd = 5v tpc 2. on resistance vs. v d (v s ) (single supply) v d , v s e v e3 5 13 on resistance e 6 0 1 5 e5 e1 2 4 3 e2 2 4 e4 0 t a = +85 c t a = +25 c t a = e40 c v dd = +5v v ss = e5v tpc 3. on resistance vs. v d (v s ) for different temperatures (dual supply)
rev. a adg619/adg620 e6e v d , v s e v 15 34 on resistance e 10 0 4 2 8 6 0 2 t a = +85 c t a = +25 c t a = e40 c 9 3 1 7 5 v dd = 5v v ss = 0v tpc 4. on resistance vs. v d (v s ) for different temperatures (single supply) v s e v e4 e3 5 0 1234 charge injection e pc 250 0 100 50 200 150 e5 e2 e1 t a = 25 c v dd +5v v ss e5v v dd 5v v ss 0v tpc 7. charge injection vs. source voltage 0.2 100 10 v dd = +5v v ss = e5v t a = 25 c 1 frequency e mhz attenuation e db e10 e20 e30 e40 e50 e60 e70 e80 tpc 10. crosstalk vs. frequency temperature e c 10 20 60 70 80 50 leakage currents e na 0.5 0.2 0.4 0.3 0 30 40 0.1 0 e0.1 e0.2 e0.3 e0.4 e0.5 0 v dd = +5v v ss = e5v v d = 4.5v v s = 4.5v i d , i s (on) i s (off) tpc 5. leakage currents vs. temperature (dual supply) temperature e c e40 e20 020 40 60 80 time e ns 180 160 0 80 60 40 20 140 100 120 v dd 5v v ss 0v v dd +5v v ss e5v v dd 5v v ss 0v v dd +5v v ss e5v t on t off tpc 8. t on /t off times vs. temperature 0.2 1000 0 10 v dd = +5v v ss = e5v t a = 25 c e2 e4 e6 e8 e10 e12 1 100 frequency e mhz attenuation e db tpc 11. on response vs. frequency temperature e c 10 20 60 70 80 50 leakage currents e na 0.5 0.2 0.4 0.3 0 30 40 0.1 0 e0.1 e0.2 e0.3 e0.4 e0.5 0 i d , i s (on) i s (off) v dd = 5v v ss = 0v v d = 4.5v/1v v s = 1v/4.5v tpc 6. leakage currents vs. temperature (single supply) 0.03 e10 110 100 v dd = +5v v ss = e5v t a = 25 c frequency e mhz alternation e db e20 e30 e40 e50 e60 e70 e80 e90 e100 tpc 9. off isolation vs. frequency
rev. a adg619/adg620 e7e test circuits i ds v1 sd v s r on = v1/i ds test circuit 1. on resistance sd v s v d i s (off) i d (off) test circuit 2. off leakage sd a v d i d (on) nc test circuit 3. on leakage v dd 0.1 f v s in sd v dd gnd r l 300 c l 35pf v out v ss 0.1 f v ss 50% 50% 90% 90% v in v out t off t on test circuit 4. switching times d v dd gnd 90% 90% 50% 50% 0v 0v v ss v dd v s1 in s1 r l2 300 c l2 35pf v out v ss 0.1 f v in v out t bbm v s2 v in s2 d2 0.1 f t bbm test circuit 5. break-before-make time delay, t bbm (adg619 only) v s1 v dd gnd v ss v dd v s1 in r l2 300 c l2 35pf v ss 0.1 f v d v in 0.1 f c l1 35pf r l1 300 50% 50% 0v v in v s1 v s2 80%v d 80%v d t mbb test circuit 6. make-before-break time delay, t mbb (adg620 only) ds v dd in v s gnd c l 1nf v out r s v dd v ss v ss v in v out v out q inj = c l v out v out s1 s2 test circuit 7. charge injection
c02617e0e6/03(a) e8e adg619/adg620 rev. a v out 50 network analyzer r l 50 in gnd s 0.1 f d 50 off isolation = 20 log v out v s 0.1 f v ss v dd v ss v in v s v dd test circuit 8. off isolation v out 50 network analyzer r l 50 in gnd v in s 0.1 f d insertion loss = 20 log v out with switch v s without switch 0.1 f v ss v dd v ss v s v dd test circuit 9. bandwidth outline dimensions 8-lead small outline transistor package [sot-23] (rt-8) dimensions shown in millimeters 1 3 5 6 2 8 4 7 2.90 bsc pin 1 1.60 bsc 1.95 bsc 0.65 bsc 0.38 0.22 0.15 max 1.30 1.15 0.90 seating plane 1.45 max 0.22 0.08 0.60 0.45 0.30 8 4 0 2.80 bsc compliant to jedec standards mo-178ba 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 0.23 0.08 0.80 0.40 8 0 85 4 1 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc compliant to jedec standards mo-187aa coplanarity 0.10 gnd v dd 0.1 f v dd v ss 0.1 f v ss s1 d s2 v s network analyzer in 50 r 50 r 50 v out channel-to-channel crosstalk = 20 log v s v out test circuit 10. channel-to-channel crosstalk revision history location page 6/03?data sheet changed from rev. 0 to rev. a. edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
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